ASIC / Physical Design Engineer (Int, Senior and Prinicipal)
- Location: Ottawa, Ontario
- Type: Direct Hire
- Job #35001
- 8+ years in ASIC Physical Design / Backend Implementation (PnR)
- End-to-end experience from netlist to GDSII (full physical design flow)
- Strong hands-on with Place & Route (floorplan, CTS, routing, optimization)
- Proven timing closure expertise (setup/hold, ECO implementation)
- Deep experience with Synopsys and/or Cadence tool suites
- Advanced node exposure (FinFET, sub-10nm / 7nm / 5nm preferred)
- Strong Static Timing Analysis (STA) and timing report analysis
- Experience with clock tree synthesis (CTS) and clock optimization
- Solid understanding of DRC/LVS and physical verification flows
- IR drop / power integrity analysis and optimization experience
- Experience optimizing PPA (power, performance, area)
- Ability to debug PnR, congestion, and tool-related issues
- Scripting skills (Tcl, Python, or similar) for automation
- Cross-functional collaboration with RTL, DFT, and analog teams
- Experience with tools such as PrimeTime, StarRC, RedHawk, Calibre (nice to have)